1. Technical Field
This embodiment relates to a concatenated error correction device, and more particularly to a concatenated error correction technique which uses two error correction codes for correcting errors in a unit of a memory page.
2. Description of Related Art
A single-level cell (SLC) memory stores 1 bit-data in one memory cell. The SLC memory is also called a single-bit cell (SBC) memory. A process for storing data in a memory cell (single-level cell) of the SLC memory is called a program process and is able to change a threshold voltage of the memory cell. For example, when a logical data of “1” is stored in the single-level cell, the single-level cell may have a threshold voltage of 1.0V, and when a logical data of “0” is stored in the single-level cell, the single-level cell may have a threshold voltage of 3.0V.
Due to the minute difference between the electrical characteristics of the single-level cells, a threshold voltage formed in each of the single level cells in which the same data has been programmed comes to have a distribution with a certain range. For example, when a voltage read from the memory cell is from 0.5V to 1.5V, the logical data stored in the memory cell may be determined as 1, and when the voltage read from the memory cell is from 2.5V to 3.5V, the logical data stored in the memory cell may be determined as 0. The data stored in the memory cell are distinguished according to a current difference and a voltage difference of the memory cell when the data are read.
Meanwhile, in response to the requirement for high integration of the memory, a multi-level cell (MLC) memory allowing two or more bit data to be programmed in one memory cell has been proposed. The MLC memory is also called a multi-bit cell (MBC) memory. However, the more the number of the bits which are programmed in one memory cell increases, the more the reliability decreases and the more the read failure rate increases. In order that the m bits are programmed in one memory cell, any one of 2m threshold voltages should be formed in the memory cell. Due to the minute difference between the electrical characteristics of the memory cells, the threshold voltages of the memory cells in which the same data has been programmed may form a distribution with a certain range. Here, one distribution of the threshold voltage may correspond to each of the 2m data values which can be generated by the m bits. However, since the voltage window of the memory is limited, a distance between the 2m distributions of the threshold voltage between the adjacent bits is reduced with the increase of m. When the distance between the distributions is more reduced, the distributions may be overlapped with each other. When the distributions are overlapped with each other, the read failure rate may increase.
For the purpose of reducing the read failure rate, error control codes or error control coding or error correction codes (ECC) are being actively used and researches are being actively devoted to how to effectively program so as to reduce errors. A memory controller controls memory access of a host. The memory controller converts a virtual memory address into an actual memory address and performs memory protection, cache management, bus arbitration, etc. In general, one page is mapped onto one address. The one page is composed of 4 to 8 words. Each word may be protected by the ECC.
Hamming code or Bose-Chadhuri-Hocquenghem (BCH) code is widely used as the ECC. However, as the read failure rate increases, there is a requirement for the ECC capable of more powerfully correcting errors.
Low density parity check (LDPC) code and Turbo code, etc., are mentioned as the ECC for the next-generation flash memory. However, the excellent error correction capability of such codes can be ensured when soft output information is given from the channel. Due to the characteristics of the flash memory, multiple readings should be carried out to obtain the soft output information. However, this causes a significant reduction of the data read speed of a system.
The BCH code having powerful error correction capability may be proposed to be used. However, regarding a BCH decoder, the decoding complexity increases rapidly with the increase of the error correction capability.
There is a need for an encoding technique and a decoding technique which are capable of significantly improving the error correction capability without requiring the soft output information and of preventing the decoding complexity from being increased.